The present invention relates generally to the field of electronic microcircuit fabrication and, more particularly, to a structure and process for reducing die corner and edge stresses in microelectronic packages.
The miniaturization of electronic microcircuits has focused attention on packaging these devices in a more efficient and reliable manner. A typical electronic microcircuit includes a microelectronic die (i.e., a silicon chip) mounted to a carrier substrate with an epoxy-based material disposed between the die and the substrate. A heat spreader (e.g., aluminum Al or copper Cu) is typically included in the package and has direct contact with the die so that heat generated by the die can dissipate by convection directly into the surrounding air.
Because there is a mismatch in the coefficients of thermal expansion (CTE) between the die and the supporting packaging materials, electronic microcircuits suffer from stress problems. For instance, silicon has a CTE of about 3 parts per million per degree Celsius (ppm/.degree. C.) while the CTE of an organic substrate is generally 16 ppm/.degree. C. and that of a ceramic substrate is about 6.5 ppm/.degree. C. One undesired effect of thermal expansion can cause the central portion of a die, secured to a substrate, to curve or bend which causes some of the electrical connections between the die and the substrate to separate. Another damaging effect caused by thermally induced curving includes cracking and/or breaking of the die. In this instance, tensile stresses occur in the outer layer of the die as it bends. If these stresses are greater than the fracture strength of the die, it chips or breaks. These same thermal effects also appear in the substrate and other packaging materials.
One method of solving this problem has been to include epoxy-based encapsulation material (i.e., underfill) between the die and the substrate. In the commonly used flip-chip device, for example, the die is mounted face-down to a wiring substrate so that conductive terminals in the die (usually in the form of solder balls) are directly physically and electrically connected to the wiring pattern on the substrate. This underfill encapsulation material bonds the die to the substrate and thus lessens the stress in the solder balls to improve the performance of the die.
A limitation with this method, however, is the potential creation of voided areas in the underfill encapsulation material. If voiding occurs, the solder balls located in the void will be subjected to the same thermal fatigue as if the underfill encapsulation material were not there. Moreover, as the industry moves toward smaller electronic microcircuits it is becoming increasingly difficult to properly insert underfill encapsulation material into the gap between the die and the substrate.
Finally, manufacturers are moving away from aluminum oxide interconnects in the die to copper low-k materials. Although copper low-k materials speed up the interconnects, they are mechanically very weak. The effects of CTE induced stress will thus be much greater in the next generation of electronic microcircuits.